Functionality of computational systems often involves access to values stored in one or more specific cells of large memory arrays. The memory array includes rows and columns of memory cells. Typically, addressing circuitry and/or signals are used to select a memory cell from the array that is associated with a specified row and column, and the value of that memory cell is passed through read-out circuitry to a shared output line. In this way, specific values can be selected from large arrays of memory cells with an appreciably reduced number of read-out lines. However, adding circuitry to the memory read-out path can negatively impact power consumption and memory access times. While addressing and read-out circuitry can be sped up by increasing clock speeds, realizing the additional clock speeds can involve consuming additional power. Accordingly, it may be desirable in many applications to provide novel techniques for speeding up the read-out of memory arrays without relying on increased power consumption.